The present invention relates to the manufacturing of semiconductor devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d -type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
A number of different variations of a dual damascene process have been employed during semiconductor manufacturing. With reference to FIGS. 1A-1L, a dual damascene process for forming vias and a second metallization level over a first metallization level, according to conventional techniques, will be described. This process can be repeated to form multiple metallization levels, i.e., two or more, stacked one on top of another.
In FIG. 1A a second barrier layer 12 is deposited over a first metallization level 10. The second barrier layer 12 acts as a passivation layer that protects the first metallization level 10 from oxidation and contamination and prevents the material of the metallization level 10 from diffusing into a subsequently formed dielectric layer. The second barrier layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the metallization level 10 to form the second barrier layer 12. An illustrative process used for depositing silicon nitride is PECVD.
In FIG. 1B, a first dielectric layer 14 is deposited over the second barrier layer 12. The first dielectric layer 14 is generally formed from silicon oxide although other acceptable materials include organic polymeric materials. Many techniques are capable of providing a dielectric layer 14 formed from silicon oxide, and an illustrative process is PECVD.
In FIG. 1C, a first barrier layer 40 is deposited over the first dielectric layer 14. The first barrier layer 40 acts as an etch stop during etching of a dielectric layer subsequently formed over the first barrier layer 40. As with the second barrier layer 12, a material typically used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the first dielectric layer 14 to form the first barrier layer 40. An illustrative process used for depositing silicon nitride is PECVD.
In FIG. 1D, a second dielectric layer 42 is deposited over the first barrier layer 40. The second dielectric layer 42 is generally formed from silicon oxide although other acceptable materials organic polymeric materials. Many techniques are capable of forming a second dielectric layer 42 formed from silicon oxide, and an illustrative process is PECVD.
In FIG. 1E, the pattern of the vias are formed in the second dielectric layer 42 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 17 over the second dielectric layer 42 and exposing and developing the resist 17 to form the desired pattern of the vias. The first etch, which is highly selective to the material of the second dielectric layer 42, removes the second dielectric layer 42 until the etchant reaches the first barrier layer 40. The first etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the second dielectric layer 42 directly below the opening in the resist 17.
In FIG. 1F, a second etch, which is highly selective to the material of the first barrier layer 40, removes the first barrier layer 40 until the etchant reaches the first dielectric layer 14. The second etch is also typically an anisotropic etch. The second etch is followed by a third etch to form the via 16. The third etch, which is highly selective to the material of the first dielectric layer 14, removes the first dielectric layer 14 until the etchant reaches the second barrier layer 12. The third etch is also typically an anisotropic etch.
In FIG. 1G, the resist 17 is removed from over the second dielectric layer 42. A typical method of removing the resist 17 is known as xe2x80x9cashingxe2x80x9d whereby the resist 17 is oxidized with an O2 plasma at room or elevated temperatures. After the resist 17 is removed, an anti-reflective material 48 is introduced into the via 16. The anti-reflective material 48, also known as BARC (bottom anti-reflective coating), can serve different functions such as protecting the second barrier layer 12 from attack and suppress interference waves and avoid standing waves during subsequent lithography processes.
In FIG. 1H, the trenches 46 are formed in the second dielectric layer 42 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 50 over the second dielectric layer 42 and exposing and developing the resist 50 to form the desired pattern of the trenches 46. A fourth etch, which is highly selective to the material of the second dielectric layer 42, removes the second dielectric layer 42 until the etchant reaches the first barrier layer 40. The fourth etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the second dielectric layer 42 directly below the opening in the resist 50.
In FIG. 1I, the anti-reflective material 48 is removed using conventional techniques. For example, the anti-reflective material 48 can be removed with a wet-etch solution comprising H2SO4/H2O2 or using an anisotropic etch with O2. After the anti-reflective material 48 is removed, a fifth etch, which is highly selective to the material of the first and second barrier layers 40, 12, then removes the second barrier layer 12 until the etchant reaches the first metallization level 10 and removes the first barrier layer 40 until the etchant reaches the first dielectric layer 14. The fifth etch is also typically an anisotropic etch.
In FIG. 1J, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a third barrier layer 20. The third barrier layer 20 acts to prevent diffusion into the first and second dielectric layers 14, 42 of the conductive material subsequently deposited into the via 16 and trench 46.
In FIG. 1K, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited in the via 16 and trench 46 and over the second dielectric layer 42. A typical process initially involves depositing a xe2x80x9cseedxe2x80x9d layer on the barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 16 and trench 46. So as to ensure complete filling of the via 16 and trench 46, the Cu-containing conductive layer 22 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer 24 so as to overfill the trench 46 and cover the upper surface 52 of the second dielectric layer 42.
In FIG. 1L, the entire excess thickness of the metal overburden layer 24 over the upper surface 52 of the second dielectric layer 42 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2O3)-based slurry, which leaves a conductive plug in the via 16 and a second metallization level in the trench 46. The second metallization level has an exposed upper surface 58, which is substantially co-planar with the upper surface 52 of the second dielectric layer 42.
A problem resulting from the use of an anti-reflective material is the formation of fencing oxides. As illustrated in FIG. 2, if the anti-reflective material 48 (not shown) extends too far above the first dielectric layer 14, when the second dielectric layer 42 is etched, an oxide xe2x80x9cfencexe2x80x9d 54 can be formed adjacent to and around the anti-reflective material 48 that extended above the first dielectric layer 14. The fence 54 results from a slower etch rate of the second dielectric layer 42 caused by the excess anti-reflective material preventing the etching process from completely reaching the areas of the second dielectric adjacent the excess anti-reflective material and also from redeposition of the second dielectric layer 42 onto the excess anti-reflective material 48.
This fence 54 can disadvantageously produce sharp corners at the opening of the via 16. For example, when the conductive material is deposited in an opening having sharp comers, the material tends to build up more quickly at the corners than on sidewalls of the via 16. Consequentially, the material at the opposing comers can form cantilevered bridges that eventually meet in the middle of the opening. When this occurs, the opening is blocked and further deposition of material within the via 16 is prevented, thereby leaving a void in the opening. The creation of such an opening can disadvantageously cause a malfunction in the semiconductor device. Accordingly, a need exists for an improved dual damascene process that prevents the problems associated with the removal of an anti-reflective material, yet still retains the benefits associated with the use of anti-reflective material.
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device. The method includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature. The conductive material and the first level can comprise copper (Cu) or a Cu alloy.
By removing a portion of the anti-reflective material before the second dielectric layer is etched, excess amounts of organic fill material extending above the via can be reduced. Excess organic fill material can accumulate oxides during the etching of the second dielectric layer, and these oxides can hamper subsequent removal of the organic fill material. If the organic fill material cannot be completely removed, the via cannot be completely filled with the conductive material. Therefore, the partial removal of the organic fill material reduces the incidence of partly filled vias.
In another aspect of the invention, the organic fill material is an anti-reflective material. Also, the portion of the organic fill material being removed includes organic fill material positioned above the first dielectric layer. Furthermore, the portion of the organic fill material removed can be at least 500 angstroms or at least 1000 angstroms. The process of removing a portion of the organic fill material can be accomplished by oxidation, and the process of completely removing the organic fill material can be accomplished by oxidation, such as dry etching.
In a further aspect of the invention, the method can further include the steps of forming a first barrier layer between the first and second dielectric layers and etching the first barrier layer after each time the second dielectric layer has been etched. Additionally, the method can further include the steps of forming a first resist over the second dielectric layer before etching to form the opening and removing the first resist before the organic fill material is deposited. Also, the method can include the steps of forming a second resist over the second dielectric layer before etching to form the trench and removing the second resist after forming the trench.